Smooth, high quality video playback should be one of the key features of portable, and low-powered devices such as PDAs, web tablets, set-top boxes, in-vehicle computers, and other embedded devices. Standards and Open Architectures are the building blocks of next generation video delivery platforms. The 3ivx MPEG-4 5.0 Core is key for bringing high quality, high performance MPEG-4 playback to such platforms and related embedded devices.

The 3ivx MPEG-4 5.0 Decoder has been tested for performance (speed) and interoperability, on an XScale development board running Linux, provided by ACUNIA Embedded Solutions. The processor is an Intel XScale processor clocked to 733 MHz (up to 800 MIPS) with a 100 MHz core memory bus.

Performance
The video decoding speed of the 3ivx MPEG-4 5.0 codec has been
benchmarked by measuring the average frame rate (Frames Per Second). In this particular test, The Matrix trailer, 640x480 encoded at 1 mBit/sec, was used. The clip was chosen because it is a high action video that stresses the decoder.

The decoding speed is measured with YUV 420 by reference output, the native 3ivx MPEG-4 5.0 output format (this is equal to core decoding speed), YUV 420 output (with a memory copy to the screen) and RGB16 output (the YUV output has to be converted from YUV420 to RGB16 and transferred to the screen, since some devices do not have a native YUV/YCrCb video chip set).

As you can see on the chart (longer is better), 3ivx MPEG-4 5.0 heavily benefits from direct YUV output. If you don't have to do the optimized YUV->RGB conversion, there is a further gain of 12 fps for YUV by reference output. Using 3ivx this XScale development board plays any 640x480, 25 fps video content fluently, regardless of which output format the device requires.

Average Frame Rate Decoding Performance of the 3ivx MPEG-4 5.0 Video Decoder on the XINGU Platform. The video being decoded is; The Matrix Trailer - Size: 640x480 - Bitrate: 1 mBit/sec

The 3ivx code can be optimized for size or speed (by decreasing the depth of the decode pipeline). The tables within the codec can be reduced further at the cost of increased lookup time. The decoder predominately operates using a very small scratch space (less than 2 KB). Optimized C Implementation The 3ivx MPEG-4 5.0 Core can easily, with minor modifications, be compiled to any platform while taking advantage of the optimized core algorithms. 3ivx MPEG-4 5.0 is completely written in ANSI C (100%) and optimized for cache locality and for minimizing data movement instructions. Critical functions were additionally rewritten to take advantage of MMX and ARM v4/XScale. Low power consumption Due to the efficiency of the 3ivx codec, it is possible to deploy it in a low powered environment. The codec is completely integer based (shifts and adds) with a very small amount of multiplies, thus not requiring expensive FPU type operations.

Low Memory Usage 3ivx requires only 143 kilobytes of RAM for QCIF sized (176x144) video (e.g. 3G phones). 100% fixed point implementation 3ivx does not use floating-point numbers, while maintaining the same quality as the floating point MPEG-4 reference implementation. This means that 3ivx runs (out of the box) on CPUs/DSPs (Digital Signal Processor) that do not have an FPU (Floating Point Unit) such as the TI C6415. Supported Tools 3ivx MPEG-4 5.0 is compliant with the MPEG-4 Simple, and Advanced Simple Profile. The codec currently supports resynch markers in the decoder as well as error detection and basic error concealment. Data Partitioning, RVLC and AIR are currently not supported.